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» Functional Validation of System Level Static Scheduling
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ICCAD
2008
IEEE
151views Hardware» more  ICCAD 2008»
14 years 4 months ago
Race analysis for SystemC using model checking
—SystemC is a system-level modeling language that offers a wide range of features to describe concurrent systems rent levels of abstraction. The SystemC standard permits simulato...
Nicolas Blanc, Daniel Kroening
ICVGIP
2008
13 years 9 months ago
Visibility Cuts: A System for Rendering Dynamic Virtual Environments
In recent years, the subject of occlusion culling of large 3D environments has received substantial contribution. However the major amount of research into the area has focussed o...
Soumyajit Deb, Ankit Gupta
CODES
2009
IEEE
14 years 11 days ago
Native MPSoC co-simulation environment for software performance estimation
Performance estimation of Multi-Processor System-On-Chip (MPa high abstraction level is required in order to perform early architecture exploration and accurate design validations...
Patrice Gerin, Mian Muhammad Hamayun, Fréd&...
RTCSA
2006
IEEE
14 years 1 months ago
Instruction Scheduling with Release Times and Deadlines on ILP Processors
ILP (Instruction Level Parallelism) processors are being increasingly used in embedded systems. In embedded systems, instructions may be subject to timing constraints. An optimisi...
Hui Wu, Joxan Jaffar, Jingling Xue
IFIP
1999
Springer
13 years 12 months ago
Management and optimization of multiple supply chains
Supply Chain Management (SCM) plans and controls the production over a group of autonomous enterprises. Process-oriented design is used to eliminate inefficiencies of the chain on...
J. Dorn