396 search results - page 57 / 80 » Functional Validation of System Level Static Scheduling |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper proposes an innovative methodology to perform and validate a Failure Mode and Effects Analysis (FMEA) at System-on-Chip (SoC) level. This is done in compliance with the...
LCPC
1994
Springer
13 years 11 months ago
1994
Springer
Data Dependence Abstractions for Loop Transformations Yi-Qing Yang Corinne Ancourt Francois Irigoin Ecole des Mines de Paris/CRI 77305 Fontainebleau Cedex France tractions of prog...
ASC
2008
13 years 7 months ago
2008
A dynamic classification using the support vector machine (SVM) technique is presented in this paper as a new `incremental' framework for multiple-classifying video stream da...
MEMOCODE
2010
IEEE
13 years 5 months ago
2010
IEEE
Electronic System Level (ESL) design manages the complexity of todays systems by using abstract models. In this context Transaction Level Modeling (TLM) is state-of-theart for desc...