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» Functional Verification of Large ASICs
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FPL
2008
Springer
110views Hardware» more  FPL 2008»
13 years 8 months ago
Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip
While there have been many reported implementations of Networks-on-Chip (NoCs) on FPGAs, they have not seen the same acceptance as NoCs on ASICs. One reason is that communication ...
Matthew Shelburne, Cameron Patterson, Peter Athana...
ISCA
2011
IEEE
313views Hardware» more  ISCA 2011»
12 years 10 months ago
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay ...
ISPD
2003
ACM
133views Hardware» more  ISPD 2003»
13 years 12 months ago
Closed form expressions for extending step delay and slew metrics to ramp inputs
: Recent years have seen significant research in finding closed form expressions for the delay of an RC circuit that improves upon the Elmore delay model. However, several of these...
Chandramouli V. Kashyap, Charles J. Alpert, Frank ...
ISSRE
2010
IEEE
13 years 5 months ago
Automata-Based Verification of Security Requirements of Composite Web Services
— With the increasing reliance of complex real-world applications on composite web services assembled from independently developed component services, there is a growing need for...
Hongyu Sun, Samik Basu, Vasant Honavar, Robyn R. L...
CADE
2009
Springer
14 years 7 months ago
Integrated Reasoning and Proof Choice Point Selection in the Jahob System - Mechanisms for Program Survival
In recent years researchers have developed a wide range of powerful automated reasoning systems. We have leveraged these systems to build Jahob, a program specification, analysis, ...
Martin C. Rinard