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ISPD
1997
ACM
105views Hardware» more  ISPD 1997»
14 years 28 days ago
Regular layout generation of logically optimized datapaths
The inherent distortion of the structural regularity of VLSI datapaths after logic optimization has until now precluded dense regular layouts of optimized datapaths despite their ...
R. X. T. Nijssen, C. A. J. van Eijk
ICML
1989
IEEE
14 years 24 days ago
Higher-Order and Modal Logic as a Framework for Explanation-Based Generalization
Logic programming provides a uniform framework in which all aspects of explanation-based generalization and learning may be defined and carried out, but first-order Horn logic i...
Scott Dietzen, Frank Pfenning
ICCAD
1997
IEEE
97views Hardware» more  ICCAD 1997»
14 years 29 days ago
Low power logic synthesis for XOR based circuits
An abundance of research e orts in low power logic synthesis have so far been focused on and or or nand nor based logic. A typical approach is to rst generate an initial multi-lev...
Unni Narayanan, C. L. Liu
FPL
2005
Springer
96views Hardware» more  FPL 2005»
14 years 2 months ago
FPGA PLB Evaluation using Quantified Boolean Satisfiability
This paper describes a novel Field Programmable Gate Array (FPGA) logic synthesis technique which determines if a logic function can be implemented in a given programmable circuit...
Andrew C. Ling, Deshanand P. Singh, Stephen Dean B...
MICAI
2007
Springer
14 years 2 months ago
On Reachability of Minimal Models of Multilattice-Based Logic Programs
In this paper some results are obtained regarding the existence and reachability of minimal fixed points for multiple-valued functions on a multilattice. The concept of inf-preser...
Jesús Medina, Manuel Ojeda-Aciego, Jorge Ru...