142 search results - page 17 / 29 » Functional test generation for non-scan sequential circuits |
118
Voted
ATS
2003
IEEE
15 years 9 months ago
2003
IEEE
Capacitive crosstalk can give rise to slowdown of signals that can propagate to a circuit output and create a functional error. A test generation methodology, called XGEN, was dev...
139
Voted
DAC
2000
ACM
16 years 4 months ago
2000
ACM
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
132
Voted
GLVLSI
2002
IEEE
15 years 8 months ago
2002
IEEE
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
161
Voted
INTEGRATION
2006
15 years 3 months ago
2006
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...
124
Voted
ATS
2003
IEEE
15 years 9 months ago
2003
IEEE
Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in function...