17967 search results - page 223 / 3594 » Functional timing optimization |
124
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TCAD
1998
15 years 2 months ago
1998
— Conventional methods for optimal sizing of wires and transistors use linear resistor-capacitor (RC) circuit models and the Elmore delay as a measure of signal delay. If the RC ...
115
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ASPDAC
2009
ACM
15 years 9 months ago
2009
ACM
Abstract— Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32nm node. DPL decomposes...
111
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ESA
2005
Springer
15 years 8 months ago
2005
Springer
Abstract. We show that optimal alphabetic binary trees can be constructed in O(n) time if the elements of the initial sequence are drawn from a domain that can be sorted in linear ...
103
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PADS
1998
ACM
15 years 6 months ago
1998
ACM
In message passing environments, the message send time is dominated by overheads that are relatively independent of the message size. Therefore, fine-grained applications (such a...
141
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SIAMCO
2011
14 years 9 months ago
2011
Abstract. A framework is introduced for the identification of controls for single-class timevarying queueing networks that are asymptotically optimal in the so-called uniform acce...