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CASES
2001
ACM
13 years 11 months ago
A system-on-a-chip lock cache with task preemption support
Intertask/interprocess synchronization overheads may be significant in a multiprocessor-shared memory System-on-a-Chip implementation. These overheads are observed in terms of loc...
Bilge Saglam Akgul, Jaehwan Lee, Vincent John Moon...
ICDCS
2010
IEEE
13 years 11 months ago
When Transportation Meets Communication: V2P over VANETs
Abstract—Information interaction is a crucial part of modern transportation activities. In this paper, we propose the idea of Vehicle-to-Passenger communication (V2P), which allo...
Nianbo Liu, Ming Liu, Jiannong Cao, Guihai Chen, W...
RTSS
2000
IEEE
13 years 11 months ago
Efficient Scheduling of Sporadic, Aperiodic, and Periodic Tasks with Complex Constraints
Many industrial applications with real-time demands are composed of mixed sets of tasks with a variety of requirements. These can be in the form of standard timing constraints, su...
Damir Isovic, Gerhard Fohler
ICCAD
1997
IEEE
137views Hardware» more  ICCAD 1997»
13 years 11 months ago
Optimization techniques for high-performance digital circuits
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
Chandramouli Visweswariah
ICIP
1995
IEEE
13 years 11 months ago
Error bound for multi-stage synthesis of narrow bandwidth Gabor filters
This paper develops an error bound for narrow bandwidth Gabor filters synthesized using multiple stages. It is shown that the error introduced by approximating narrow bandwidth Ga...
R. Neil Braithwaite, Bir Bhanu
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