694 search results - page 13 / 139 » Gate Sizing Using a Statistical Delay Model |
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after...
GLVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
—Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effectiv...
ANSS
2003
IEEE
14 years 1 months ago
2003
IEEE
In this work, we present a computational behavioral model for logic gates called Internode (Internal Node Logic Computational Model) that considers the functionality of the gate a...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
Traditional timing variation reduction techniques are only able to decrease the gate delay variation by incurring a delay overhead. In this work, we propose novel and effective sp...
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
Abstract— This paper presents a post-route gate-sizing algorithm for coupling-noise reduction that constrains the yield loss under process variations. Algorithms for coupling-noi...