694 search results - page 19 / 139 » Gate Sizing Using a Statistical Delay Model |
DAC
2005
ACM
14 years 8 months ago
2005
ACM
Recent study shows that the existing first order canonical timing model is not sufficient to represent the dependency of the gate delay on the variation sources when processing an...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
— Decoupling capacitors (decaps) are typically used to reduce the noise in the power supply network. Because the delay of gates and interconnects is affected by the supply voltag...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
— Process variations in digital circuits make sequential circuit timing validation an extremely challenging task. In this paper, a Statistical Bellman-Ford (SBF) algorithm is pro...
VLSISP
2008
13 years 7 months ago
2008
Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering ...