694 search results - page 21 / 139 » Gate Sizing Using a Statistical Delay Model |
TCAD
2010
13 years 6 months ago
2010
—With the scaling of complementary metal–oxide– semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacit...
DAC
1999
ACM
14 years 8 months ago
1999
ACM
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...
ICCCN
2007
IEEE
14 years 2 months ago
2007
IEEE
Abstract— This work is concerned with definining a performance index that can be used as an objective measure in the evaluation and comparison of ad hoc networking protocols. Sp...
ISQED
2006
IEEE
14 years 1 months ago
2006
IEEE
Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. This paper develops closed-form models to predict the dela...
ISVLSI
2007
IEEE
14 years 2 months ago
2007
IEEE
In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of e...