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» Gate Sizing Using a Statistical Delay Model
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ICCD
2004
IEEE
120views Hardware» more  ICCD 2004»
14 years 4 months ago
XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs
This paper describes XTalkDelay, an industrial-strength methodology and tool for measuring the impact of crosstalk on delays of paths in a design. The main cornerstone of XTalkDel...
Yinghua Li, Rajeev Murgai, Takashi Miyoshi, Ashwin...
ASPDAC
2006
ACM
105views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Speed binning aware design methodology to improve profit under parameter variations
—Designing high-performance systems with high yield under parameter variations has raised serious design challenges in nanometer technologies. In this paper, we propose a profit-...
Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saib...
CSDA
2010
67views more  CSDA 2010»
13 years 7 months ago
Using combinatorial optimization in model-based trimmed clustering with cardinality constraints
Statistical clustering criteria with free scale parameters and unknown cluster sizes are inclined to create small, spurious clusters. To mitigate this tendency a statistical model ...
María Teresa Gallegos, Gunter Ritter
WCNC
2008
IEEE
14 years 2 months ago
Throughput and Delay Performance Analysis of Packet Aggregation Scheme for PRMA
—Packet reservation multiple access (PRMA) protocol is an implicit reservation MAC protocol. It is initially designed for voice packets in the cellular networks [2], [3] but it is...
Qi Zhang, Villy Bæk Iversen, Frank H. P. Fit...
DAC
2008
ACM
14 years 8 months ago
On the role of timing masking in reliable logic circuit design
Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking ...
Smita Krishnaswamy, Igor L. Markov, John P. Hayes