694 search results - page 30 / 139 » Gate Sizing Using a Statistical Delay Model |
ATS
2009
IEEE
13 years 6 months ago
2009
IEEE
Negative bias temperature instability (NBTI) has been a significant reliability concern in current digital circuit design due to its effect of increasing the path delay with time a...
CVPR
2012
IEEE
11 years 11 months ago
2012
IEEE
The use of statistical pattern recognition models to segment the left ventricle of the heart in ultrasound images has gained substantial attention over the last few years. The mai...
ISCAS
2006
IEEE
14 years 3 months ago
2006
IEEE
– This paper addresses the problem of ordering and sizing parallel wires in a single metal layer within an interconnect channel of a given width, such that crosscapacitances are ...
ASPDAC
2010
ACM
13 years 6 months ago
2010
ACM
This paper describes gate work function and oxide thickness tuning to realize novel circuits using dual-Vth independent-gate FinFETs. Dual-Vth FinFETs with independent gates enabl...
WCNC
2008
IEEE
14 years 3 months ago
2008
IEEE
—UWB technology can reach centimetre level ranging and positioning accuracy in LOS propagation when time of arrival techniques are used. However, in a real positioning system, th...