694 search results - page 31 / 139 » Gate Sizing Using a Statistical Delay Model |
IEAAIE
1999
Springer
14 years 1 months ago
1999
Springer
This paper introduces a new approach in the debugging of hardware designs. The design is given as a VHDL program and converted in a component connection model. The conversion is si...
DAC
2006
ACM
14 years 10 months ago
2006
ACM
The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. ...
MCU
1998
13 years 10 months ago
1998
A reversible cellular automaton (RCA) is a cellular automaton (CA) whose global function is injective and every configuration has at most one predecessor. Margolus showed that the...
ITC
2003
IEEE
14 years 2 months ago
2003
IEEE
A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of...
ICCAD
1993
IEEE
14 years 1 months ago
1993
IEEE
We have proposed an e cient measure to reduce the clock skew by assigning the clock network with variable branch widths. This measure has long been used for \H" clock tree. T...