694 search results - page 33 / 139 » Gate Sizing Using a Statistical Delay Model |
ISCAS
2006
IEEE
14 years 3 months ago
2006
IEEE
— In this paper we propose a new metric called “effective tunneling capacitance” (Ct eff ) to quantify the transient swing in the gate leakage (gate oxide tunneling) current ...
ATS
2003
IEEE
14 years 2 months ago
2003
IEEE
Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in function...
SIGCOMM
1995
ACM
14 years 15 days ago
1995
ACM
In most network models for quality of service support, the communication links interconnecting the switches and gateways are assumed to have fixed bandwidth and zero error rate. T...
BMCBI
2008
13 years 9 months ago
2008
Background: Gene expression profiling has the potential to unravel molecular mechanisms behind gene regulation and identify gene targets for therapeutic interventions. As microarr...
ASPDAC
2006
ACM
14 years 3 months ago
2006
ACM
—For nanoscale interconnection, the scattering effect will soon become prominent due to scaling. It will increase the effective resistivity and thus interconnection delay signifi...