694 search results - page 54 / 139 » Gate Sizing Using a Statistical Delay Model |
ICCAD
2006
IEEE
14 years 6 months ago
2006
IEEE
Statistical static timing analysis (SSTA) has become a key method for analyzing the effect of process variation in aggressively scaled CMOS technologies. Much research has focused...
MOBIHOC
2006
ACM
14 years 8 months ago
2006
ACM
The performance of a multihop wireless network is typically affected by the interference caused by transmissions in the same network. In a statistical fading environment, the inte...
INFOCOM
2010
IEEE
13 years 7 months ago
2010
IEEE
We investigate the fundamental capacity limits of space-time journeys of information in mobile and Delay Tolerant Networks (DTNs), where information is either transmitted or carrie...
DAC
2009
ACM
14 years 10 months ago
2009
ACM
Embedded cryptosystems show increased vulnerabilities to implementation attacks such as power analysis. CMOS technology trends are causing increased process variations which impac...
TVLSI
2008
13 years 9 months ago
2008
Abstract--The quantum-dot cellular automata (QCA) model offers a novel nano-domain computing architecture by mapping the intended logic onto the lowest energy configuration of a co...