38 search results - page 7 / 8 » Gate sizing with controlled displacement |
FCCM
2006
IEEE
14 years 1 months ago
2006
IEEE
The growth in size and performance of Field Programmable Gate Arrays (FPGAs) has compelled System-on-aProgrammable-Chip (SoPC) designers to use soft processors for controlling sys...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...
CHES
2009
Springer
14 years 7 months ago
2009
Springer
Algebraic side-channel attacks have been recently introduced as a powerful cryptanalysis technique against block ciphers. These attacks represent both a target algorithm and its ph...
ICC
2007
IEEE
14 years 1 months ago
2007
IEEE
—A H-WRR (Hierarchical Weighted Round-Robin) EPON (Ethernet Passive Optical Network) DBA (Dynamic Bandwidth Allocation) algorithm is devised and investigated. WRR table entries h...
ICCAD
1997
IEEE
13 years 11 months ago
1997
IEEE
This paper is concerned with approximate delay computation algorithms for combinational circuits. As a result of intensive research in the early 90’s [3, 8] efficient tools exi...