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VLSID
2007
IEEE
85views VLSI» more  VLSID 2007»
14 years 7 months ago
Metrics to Quantify Steady and Transient Gate Leakage in Nanoscale Transistors: NMOS vs. PMOS Perspective
In this paper we explore the use of a set of novel design metrics for characterizing the impact of gate oxide tunneling current in nanometer CMOS devices and perform Monte Carlo s...
Elias Kougianos, Saraju P. Mohanty
ERSA
2006
76views Hardware» more  ERSA 2006»
13 years 8 months ago
Logic Synthesis and Place-and-Route Environment for ORGAs
Abstract-- We have continued development of Optically Reconfigurable Gate Arrays (ORGAs) to realize larger virtual gate count VLSIs than currently available VLSIs. The grain and st...
Minoru Watanabe, Fuminori Kobayashi
TVLSI
2010
13 years 2 months ago
Asynchronous Current Mode Serial Communication
Abstract--An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the di...
Rostislav (Reuven) Dobkin, Michael Moyal, Avinoam ...
ICCD
2004
IEEE
154views Hardware» more  ICCD 2004»
14 years 4 months ago
Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits
Gate oxide tunneling current (Igate) is emerging as a key roadblock for device scaling in nanometer-scale CMOS circuits. A practical means to reduce Igate is to leverage dual Tox ...
Anup Kumar Sultania, Dennis Sylvester, Sachin S. S...
ISQED
2006
IEEE
109views Hardware» more  ISQED 2006»
14 years 1 months ago
Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher perm...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...