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GLVLSI
2007
IEEE
171views VLSI» more  GLVLSI 2007»
14 years 1 months ago
Combinational equivalence checking for threshold logic circuits
Threshold logic is gaining prominence as an alternative to Boolean logic. The main reason for this trend is the availability of devices that implement these circuits efficiently (...
Tejaswi Gowda, Sarma B. K. Vrudhula, Goran Konjevo...
NOSSDAV
2004
Springer
14 years 26 days ago
Reduced state fair queuing for edge and core routers
Despite many years of research, fair queuing still faces a number of implementation challenges in high speed routers. In particular, in spite of proposals such as DiffServ, the st...
Ramana Rao Kompella, George Varghese
CODES
2007
IEEE
14 years 1 months ago
Reliable multiprocessor system-on-chip synthesis
This article presents a multiprocessor system-on-chip synthesis (MPSoC) algorithm that optimizes system mean time to failure. Given a set of directed acyclic periodic graphs of co...
Changyun Zhu, Zhenyu (Peter) Gu, Robert P. Dick, L...
MST
2010
146views more  MST 2010»
13 years 2 months ago
The Cache-Oblivious Gaussian Elimination Paradigm: Theoretical Framework, Parallelization and Experimental Evaluation
We consider triply-nested loops of the type that occur in the standard Gaussian elimination algorithm, which we denote by GEP (or the Gaussian Elimination Paradigm). We present tw...
Rezaul Alam Chowdhury, Vijaya Ramachandran
DAC
2006
ACM
14 years 8 months ago
Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty
Existing approaches to timing analysis under uncertainty are based on restrictive assumptions. Statistical STA techniques assume that the full probabilistic distribution of parame...
Wei-Shen Wang, Vladik Kreinovich, Michael Orshansk...