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ITC
1996
IEEE
78views Hardware» more  ITC 1996»
14 years 1 months ago
Realistic-Faults Mapping Scheme for the Fault Simulation of Integrated Analogue CMOS Circuits
common use is the distinction into two (abstract) fault models: A new fault modelling scheme for integrated analogue general the "Single Hard Fault Model (SHFM)" and the ...
Michael J. Ohletz
CONEXT
2007
ACM
14 years 1 months ago
On the cost of caching locator/ID mappings
Very recent activities in the IETF and in the Routing Research Group (RRG) of the IRTG focus on defining a new Internet architecture, in order to solve scalability issues related ...
Luigi Iannone, Olivier Bonaventure
CIKM
2008
Springer
13 years 11 months ago
Mapping enterprise entities to text segments
Today, valuable business information is increasingly stored as unstructured data (documents, emails, etc.). For example, documents exchanged between business partners capture info...
Falk Brauer, Alexander Löser, Hong-Hai Do
CODES
2005
IEEE
13 years 11 months ago
An efficient direct mapped instruction cache for application-specific embedded systems
Caches may consume half of a microprocessor’s total power and cache misses incur accessing off-chip memory, which is both time consuming and energy costly. Therefore, minimizing...
Chuanjun Zhang
AVI
2010
13 years 10 months ago
3D attentional maps: aggregated gaze visualizations in three-dimensional virtual environments
Gaze visualizations hold the potential to facilitate usability studies of interactive systems. However, visual gaze analysis in threedimensional virtual environments still lacks m...
Sophie Stellmach, Lennart Nacke, Raimund Dachselt