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MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 3 months ago
Virtually Pipelined Network Memory
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
Banit Agrawal, Timothy Sherwood
ACMMSP
2006
ACM
252views Hardware» more  ACMMSP 2006»
14 years 3 months ago
Deconstructing process isolation
Most operating systems enforce process isolation through hardware protection mechanisms such as memory segmentation, page mapping, and differentiated user and kernel instructions....
Mark Aiken, Manuel Fähndrich, Chris Hawblitze...
ASPDAC
2006
ACM
120views Hardware» more  ASPDAC 2006»
14 years 3 months ago
A novel framework for multilevel full-chip gridless routing
— Due to its great flexibility, gridless routing is desirable for nanometer circuit designs that use variable wire widths and spacings. Nevertheless, it is much more difficult ...
Tai-Chen Chen, Yao-Wen Chang, Shyh-Chang Lin
ASPLOS
2006
ACM
14 years 3 months ago
A spatial path scheduling algorithm for EDGE architectures
Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed mi...
Katherine E. Coons, Xia Chen, Doug Burger, Kathryn...
CASES
2006
ACM
14 years 3 months ago
Supporting precise garbage collection in Java Bytecode-to-C ahead-of-time compiler for embedded systems
A Java bytecode-to-C ahead-of-time compiler (AOTC) can improve the performance of a Java virtual machine (JVM) by translating bytecode into C code, which is then compiled into mac...
Dong-Heon Jung, Sung-Hwan Bae, Jaemok Lee, Soo-Moo...