3131 search results - page 48 / 627 » Generalized connection caching |
MICRO
2009
IEEE
14 years 3 months ago
2009
IEEE
Efficient memory hierarchy design is critical due to the increasing gap between the speed of the processors and the memory. One of the sources of inefficiency in current caches is...
IMA
2009
Springer
14 years 3 months ago
2009
Springer
Cache timing attacks are a class of side-channel attacks that is applicable against certain software implementations. They have generated significant interest when demonstrated ag...
GLVLSI
2008
IEEE
14 years 3 months ago
2008
IEEE
Share of leakage in cache memories is increasing with technology scaling. Studies show that most stored bits in instruction caches are zero, and hence, asymmetric SRAM cells which...
SIGMETRICS
2005
ACM
14 years 2 months ago
2005
ACM
A fundamental challenge in improving the file system performance is to design effective block replacement algorithms to minimize buffer cache misses. Despite the well-known int...
DAC
2009
ACM
14 years 1 months ago
2009
ACM
Dynamic binary translation (DBT) can be used to address important issues in embedded systems. DBT systems store translated code in a software-managed code cache. Unlike general-pu...