Adaptive line placement with the set balancing cache

Efficient memory hierarchy design is critical due to the increasing gap between the speed of the processors and the memory. One of the sources of inefficiency in current caches is the non-uniform distribution of the memory accesses on the cache sets. Its consequence is that while some cache sets may have working sets that are far from fitting in them, other sets may be underutilized because their working set has fewer lines than the set. In this paper we present a technique that aims to balance the pressure on the cache sets by detecting when it may be beneficial to associate sets, displacing lines from stressed sets to underutilized ones. This new technique, called Set Balancing Cache or SBC, achieved an average reduction of 13% in the miss rate of ten benchmarks from the SPEC CPU2006 suite, resulting in an average IPC improvement of 5%. Categories and Subject Descriptors: B.3.2 [Memory Structures]: Design Styles—cache memories General Terms: Design, Performance

• Type: Conference
• Year: 2009
• Where: MICRO
• Authors: Dyer Rolán, Basilio B. Fraguela, Ramon Doallo
• Keywords: Cache Sets, Efficient Memory Hierarchy, Hardware, MICRO 2009, Working Set