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» Generating Compiler Optimizations from Proofs
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IACR
2011
97views more  IACR 2011»
12 years 7 months ago
Two-Output Secure Computation with Malicious Adversaries
We present a method to compile Yao’s two-player garbled circuit protocol into one that is secure against malicious adversaries that relies on witness indistinguishability. Our ap...
Abhi Shelat, Chih-Hao Shen
TCAD
2011
13 years 2 months ago
High-Level Synthesis for FPGAs: From Prototyping to Deployment
—Escalating system-on-chip design complexity is the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early...
Jason Cong, Bin Liu, Stephen Neuendorffer, Juanjo ...
ICCAD
2003
IEEE
98views Hardware» more  ICCAD 2003»
14 years 4 months ago
Achieving Design Closure Through Delay Relaxation Parameter
Current design automation methodologies are becoming incapable of achieving design closure especially in the presence of deep submicron effects. This paper addresses the issue of ...
Ankur Srivastava, Seda Ogrenci Memik, Bo-Kyung Cho...
PDPTA
2007
13 years 9 months ago
Suppressing Independent Loops in Packing/Unpacking Loop Nest to Reduce Message Size for Message-passing Code
- In this paper we experiment with two optimization techniques we are considering implementing in a parallelizing compiler that generates parallel code for a distributed-memory sys...
P. Jerry Martin, Clayton S. Ferner
FCCM
2002
IEEE
174views VLSI» more  FCCM 2002»
14 years 24 days ago
PAM-Blox II: Design and Evaluation of C++ Module Generation for Computing with FPGAs
This paper explores the implications of integrating flexible module generation into a compiler for FPGAs. The objective is to improve the programmabilityof FPGAs, or in other wor...
Oskar Mencer