Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...
Abstract. An approach based on term rewriting techniques for the automated termination analysis of imperative programs operating on integers is presented. An imperative program is ...
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
Abstract. Theorem provers, model checkers, static analyzers, test generators. . . all of these and many other kinds of formal methods tools can contribute to the analysis and devel...
In this paper, we present the integration of controller synthesis techniques in the SIGNAL environment through the description of a tool dedicated to the incremental construction o...