1262 search results - page 15 / 253 » Generating instruction sets and microarchitectures from appl... |
MICRO
1991
IEEE
13 years 11 months ago
1991
IEEE
This paper examines two alternative approaches to supporting code scheduling for multiple-instruction-issue processors. One is to provide a set of non-trapping instructions so tha...
IISWC
2006
IEEE
14 years 1 months ago
2006
IEEE
— Understanding the behavior of emerging workloads is important for designing next generation microprocessors. For addressing this issue, computer architects and performance anal...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex Family of FPGAs. The i...
ICPPW
2006
IEEE
14 years 1 months ago
2006
IEEE
In retargeting loop-based code for multimedia instruction set extensions, a critical issue is that vector data types of mixed precision within a loop body complicate the paralleli...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular ap...