1262 search results - page 9 / 253 » Generating instruction sets and microarchitectures from appl... |
DAC
2004
ACM
14 years 8 months ago
2004
ACM
As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communicat...
MICRO
1993
IEEE
13 years 11 months ago
1993
IEEE
The conventional classification of inter-instruction dependencies (data, anti and output dependencies) provides a basic scheme for the analysis of pipeline hazards in pipelined in...
CC
2008
Springer
13 years 9 months ago
2008
Springer
This paper describes the design and implementation of a language for specifying the semantics of an instruction set, along with a run-time system to support the static analysis of ...
ISCA
2002
IEEE
13 years 12 months ago
2002
IEEE
The number of pipeline stages separating dynamic instruction scheduling from instruction execution has increased considerably in recent out-of-order microprocessor implementations...
GLVLSI
2010
IEEE
14 years 3 days ago
2010
IEEE
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture leve...