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» Generation of BDDs from hardware algorithm descriptions
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SAMOS
2010
Springer
13 years 6 months ago
Accelerating high-level engineering computations by automatic compilation of Geometric Algebra to hardware accelerators
Abstract—Geometric Algebra (GA), a generalization of quaternions, is a very powerful form for intuitively expressing and manipulating complex geometric relationships common to en...
Jens Huthmann, Peter Muller, Florian Stock, Dietma...
CISS
2011
IEEE
12 years 11 months ago
Hardware accelerated visual attention algorithm
— We present a hardware-accelerated implementation of a bottom-up visual attention algorithm. This algorithm generates a multi-scale saliency map from differences in image intens...
Polina Akselrod, Faye Zhao, Ifigeneia Derekli, Cl&...
FPGA
2008
ACM
146views FPGA» more  FPGA 2008»
13 years 9 months ago
FPGA-optimised high-quality uniform random number generators
This paper introduces a method of constructing random number generators from four of the basic primitives provided by FPGAs: Flip-Flips, Lookup-Tables, Shift Registers, and RAMs. ...
David B. Thomas, Wayne Luk
ICMCS
2007
IEEE
149views Multimedia» more  ICMCS 2007»
14 years 2 months ago
Ground-Truthed Video Generation from Symbolic Information
An algorithm is presented that automatically generates groundtruthed video from a symbolic description for an object and a specification for the movement of a handheld video camer...
Andrew Lookingbill, Emilio R. Antúnez, Bern...
ICCD
2005
IEEE
165views Hardware» more  ICCD 2005»
14 years 4 months ago
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation
Presently, Architecture Description Languages (ADLs) are widely used to raise the abstraction level of the design space exploration of Application Specific Instruction-set Proces...
Ernst Martin Witte, Anupam Chattopadhyay, Oliver S...