647 search results - page 13 / 130 » Generation of BDDs from hardware algorithm descriptions |
ENGL
2008
13 years 8 months ago
2008
With the advent of System-On-Chip (SOC) technology, there is a pressing need to enhance the quality of ools available and increase the level of abstraction at which hardware is des...
DATE
2000
IEEE
14 years 7 days ago
2000
IEEE
This paper describes an efficient error simulator able to analyze functional VHDL descriptions. The proposed simulation environment can be based on commercial VHDL simulators. Al...
ISMVL
2009
IEEE
14 years 2 months ago
2009
IEEE
Using concepts from rough set theory we investigate the existence of approximative descriptions of collections of objects that can be extracted from data sets, a problem of intere...
ATVA
2007
Springer
14 years 2 months ago
2007
Springer
Fault tree analysis is a traditional and well-established technique for analyzing system design and robustness. Its purpose is to identify sets of basic events, called cut sets, wh...
ICCAD
1994
IEEE
13 years 12 months ago
1994
IEEE
We examine the implications of a new hazard-free combinational logic synthesis method [8], which generates multiplexor trees from binary decision diagrams (BDDs) -- representation...