647 search results - page 22 / 130 » Generation of BDDs from hardware algorithm descriptions |
IWSOC
2003
IEEE
14 years 1 months ago
2003
IEEE
The availability of high-level design entry tooling is crucial for the viability of any reconfigurable SoC architecture. This paper presents a template generation method to extra...
FCCM
2002
IEEE
14 years 24 days ago
2002
IEEE
To fully realize the benefits of partial and rapid reconfiguration of field-programmable devices, we often need to dynamically schedule computing tasks and generate instance-sp...
SASP
2009
IEEE
14 years 2 months ago
2009
IEEE
—This paper presents a parallelized architecture for hardware acceleration of multi-view face detection. In our architecture, the multi-view face detection system generates rotat...
ARC
2008
Springer
13 years 9 months ago
2008
Springer
Abstract. This paper presents a real time parallel hardware architecture for image feature detection based on the SIFT (Scale Invariant Feature Transform) algorithm. This architect...
DATE
1999
IEEE
14 years 5 days ago
1999
IEEE
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...