Sciweavers

647 search results - page 36 / 130
» Generation of BDDs from hardware algorithm descriptions
Sort
View
HPCA
2009
IEEE
14 years 8 months ago
Eliminating microarchitectural dependency from Architectural Vulnerability
The Architectural Vulnerability Factor (AVF) of a hardware structure is the probability that a fault in the structure will affect the output of a program. AVF captures both microa...
Vilas Sridharan, David R. Kaeli
ASPLOS
1991
ACM
13 years 11 months ago
Code Generation for Streaming: An Access/Execute Mechanism
Access/execute architectures have several advantages over more traditional architectures. Because address generation and memory access are decoupled from operand use, memory laten...
Manuel E. Benitez, Jack W. Davidson
DAC
2005
ACM
14 years 8 months ago
Automatic generation of customized discrete fourier transform IPs
This paper presents a parameterized soft core generator for the discrete Fourier transform (DFT). Reusable IPs of digital signal processing (DSP) kernels are important time-saving...
Grace Nordin, Peter A. Milder, James C. Hoe, Marku...
ICDT
2011
ACM
187views Database» more  ICDT 2011»
12 years 11 months ago
The PADS project: an overview
The goal of the PADS project, which started in 2001, is to make it easier for data analysts to extract useful information from ad hoc data files. This paper does not report new r...
Kathleen Fisher, David Walker
DATE
2008
IEEE
93views Hardware» more  DATE 2008»
14 years 2 months ago
A Fast Approximation Algorithm for MIN-ONE SAT
In this paper, we propose a novel approximation algorithm (RelaxSAT) for MIN-ONE SAT. RelaxSAT generates a set of constraints from the objective function to guide the search. The ...
Lei Fang, Michael S. Hsiao