647 search results - page 3 / 130 » Generation of BDDs from hardware algorithm descriptions |
ICCD
2003
IEEE
14 years 4 months ago
2003
IEEE
Functional symmetries provide significant benefits for multiple tasks in synthesis and verification. Many applications require the manual specification of symmetries using spe...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
Methods based on Boolean satisfiability (SAT) typically use a Conjunctive Normal Form (CNF) representation of the Boolean formula, and exploit the structure of the given problem ...
JSA
2007
13 years 7 months ago
2007
This paper presents a multi-language framework to FPGA hardware development which aims to satisfy the dual requirement of high level hardware design and efficient hardware impleme...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
The increasing popularity of SAT and BDD techniques in verification and synthesis encourages the search for additional speed-ups. Since typical SAT and BDD algorithms are exponent...