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» Generation of BDDs from hardware algorithm descriptions
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IEEEPACT
2006
IEEE
14 years 1 months ago
Program generation for the all-pairs shortest path problem
A recent trend in computing are domain-specific program generators, designed to alleviate the effort of porting and reoptimizing libraries for fast-changing and increasingly com...
Sung-Chul Han, Franz Franchetti, Markus Püsch...
COLING
1996
13 years 9 months ago
Reversible delayed lexical choice in a bidirectional framework
We describe a bidirectional framework for natural language parsing and generation, using a typedfeatureformalismand an HPSG-based grammar with a parser and generator derived from ...
Graham Wilcock, Yuji Matsumoto
ICS
2005
Tsinghua U.
14 years 1 months ago
Multigrain parallel Delaunay Mesh generation: challenges and opportunities for multithreaded architectures
Given the importance of parallel mesh generation in large-scale scientific applications and the proliferation of multilevel SMTbased architectures, it is imperative to obtain ins...
Christos D. Antonopoulos, Xiaoning Ding, Andrey N....
RSP
2003
IEEE
149views Control Systems» more  RSP 2003»
14 years 1 months ago
Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA
In this paper, an efficient design flow integrating Mentor Graphics Precesion C and HDL designer is derived. In this hybrid prototyping environment, efficient FPGA architectures a...
Yuanbin Guo, Gang Xu, Dennis McCain, Joseph R. Cav...
ASPDAC
1998
ACM
91views Hardware» more  ASPDAC 1998»
14 years 5 days ago
Curvilinear Detailed Routing Algorithm and Its Extension to Wire-Spreading and Wire-Fattening
— This article describes an algorithm for curvilinear detailed routing. We significantly improved the average time performance of Gao’s algorithm by resolving its bottleneck r...
Toshiyuki Hama, Hiroaki Etoh