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» Generation of BDDs from hardware algorithm descriptions
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IJCAI
2007
13 years 9 months ago
Compiling Bayesian Networks by Symbolic Probability Calculation Based on Zero-Suppressed BDDs
Compiling Bayesian networks (BNs) is one of the hot topics in the area of probabilistic modeling and processing. In this paper, we propose a new method of compiling BNs into multi...
Shin-ichi Minato, Ken Satoh, Taisuke Sato
DATE
2000
IEEE
124views Hardware» more  DATE 2000»
14 years 6 days ago
On the Generation of Multiplexer Circuits for Pass Transistor Logic
Pass Transistor Logic has attracted more and more interest during last years, since it has proved to be an attractive alternative to static CMOS designs with respect to area, perf...
Christoph Scholl, Bernd Becker
CASES
2007
ACM
13 years 11 months ago
Compiler generation from structural architecture descriptions
With increasing complexity of modern embedded systems, the availability of highly optimizing compilers becomes more and more important. At the same time, application specific inst...
Florian Brandner, Dietmar Ebner, Andreas Krall
ISLPED
1997
ACM
83views Hardware» more  ISLPED 1997»
13 years 12 months ago
A symbolic algorithm for low-power sequential synthesis
We present an algorithm that restructures the state transition graph STG of a sequential circuit so as to reduce power dissipation. The STG is modi ed without changing the behav...
Balakrishna Kumthekar, In-Ho Moon, Fabio Somenzi
VLSID
2005
IEEE
140views VLSI» more  VLSID 2005»
14 years 8 months ago
Variable Resizing for Area Improvement in Behavioral Synthesis
High level synthesis tools transform an algorithmic description to a register transfer language (RTL) description of the hardware. The algorithm behavior is typically described in...
R. Gopalakrishnan, Rajat Moona