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» Generation of BDDs from hardware algorithm descriptions
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DAC
2003
ACM
14 years 9 months ago
Coverage directed test generation for functional verification using bayesian networks
Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or...
Shai Fine, Avi Ziv
DATE
2006
IEEE
127views Hardware» more  DATE 2006»
14 years 2 months ago
ASIP design and synthesis for non linear filtering in image processing
This paper presents an Application Specific Instruction Set Processor (ASIP) design for the implementation of a class of nonlinear image processing algorithms, the Retinex-like fi...
Luca Fanucci, Michele Cassiano, Sergio Saponara, D...
ICML
2001
IEEE
14 years 8 months ago
Learning to Generate Fast Signal Processing Implementations
A single signal processing algorithm can be represented by many mathematically equivalent formulas. However, when these formulas are implemented in code and run on real machines, ...
Bryan Singer, Manuela M. Veloso
HICSS
2003
IEEE
184views Biometrics» more  HICSS 2003»
14 years 1 months ago
Content Based File Type Detection Algorithms
Identifying the true type of a computer file can be a difficult problem. Previous methods of file type recognition include fixed file extensions, fixed “magic numbers” stored ...
Mason McDaniel, Mohammad Hossain Heydari
KI
2002
Springer
13 years 7 months ago
Representation of Behavioral Knowledge for Planning and Plan-Recognition in a Cognitive Vision System
The algorithmic generation of textual descriptions of image sequences requires conceptual knowledge. In our case, a stationary camera recorded image sequences of road traffic scene...
Michael Arens, Hans-Hellmut Nagel