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» Generation of BDDs from hardware algorithm descriptions
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BMCBI
2004
104views more  BMCBI 2004»
13 years 7 months ago
Discriminative topological features reveal biological network mechanisms
Background: Recent genomic and bioinformatic advances have motivated the development of numerous network models intending to describe graphs of biological, technological, and soci...
Manuel Middendorf, Etay Ziv, Carter Adams, Jen Hom...
ISCAS
1999
IEEE
85views Hardware» more  ISCAS 1999»
14 years 8 days ago
Equivalence classes of clone circuits for physical-design benchmarking
To provide a better understanding of physical design algorithms and the underlying circuit architecture they are targeting, we need to exercise the algorithms and architectures wi...
Michael D. Hutton, Jonathan Rose
SBCCI
2005
ACM
114views VLSI» more  SBCCI 2005»
14 years 1 months ago
Traffic generation and performance evaluation for mesh-based NoCs
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these ...
Leonel Tedesco, Aline Mello, Diego Garibotti, Ney ...
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
14 years 2 months ago
Equivalence verification of arithmetic datapaths with multiple word-length operands
Abstract: This paper addresses the problem of equivalence veriļ¬cation of RTL descriptions that implement arithmetic computations (add, mult, shift) over bitvectors that have diļ¬...
Namrata Shekhar, Priyank Kalla, Florian Enescu
SIGOPS
2010
89views more  SIGOPS 2010»
13 years 6 months ago
Incremental learning of system log formats
System logs come in a large and evolving variety of formats, many of which are semi-structured and/or non-standard. As a consequence, off-the-shelf tools for processing such logs ...
Kenny Qili Zhu, Kathleen Fisher, David Walker