In this paper, a hardware implementation of the AES128 encryption algorithm is proposed. A unique feature of the proposed pipelined design is that the round keys, which are consum...
This paper considers the testability implications of low power design methodologies. Low power and high testability are shown to be highly contrasting requirements, and an optimiz...
Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Mau...
In recent years backtrack search SAT solvers have been the subject of dramatic improvements. These improvements allowed SAT solvers to successfully replace BDDs in many areas of f...
Graded-CTL is an extension of CTL with graded quantifiers which allow to reason about either at least or all but any number of possible futures. In this paper we show an extension...
Abstract—This paper presents a technique to perform arbitrary fixed permutations on streaming data. We describe a parameterized architecture that takes as input n data points st...