Sciweavers

647 search results - page 8 / 130
» Generation of BDDs from hardware algorithm descriptions
Sort
View
CATA
2010
13 years 8 months ago
A Hardware Implementation of the Advanced Encryption Standard (AES) Algorithm using SystemVerilog
In this paper, a hardware implementation of the AES128 encryption algorithm is proposed. A unique feature of the proposed pipelined design is that the round keys, which are consum...
Bahram Hakhamaneshi, Behnam S. Arad
ATS
1997
IEEE
89views Hardware» more  ATS 1997»
14 years 1 days ago
Guaranteeing Testability in Re-encoding for Low Power
This paper considers the testability implications of low power design methodologies. Low power and high testability are shown to be highly contrasting requirements, and an optimiz...
Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Mau...
MTV
2003
IEEE
126views Hardware» more  MTV 2003»
14 years 1 months ago
Heuristic Backtracking Algorithms for SAT
In recent years backtrack search SAT solvers have been the subject of dramatic improvements. These improvements allowed SAT solvers to successfully replace BDDs in many areas of f...
Ateet Bhalla, Inês Lynce, José T. de ...
CAV
2010
Springer
282views Hardware» more  CAV 2010»
13 years 11 months ago
A NuSMV Extension for Graded-CTL Model Checking
Graded-CTL is an extension of CTL with graded quantifiers which allow to reason about either at least or all but any number of possible futures. In this paper we show an extension...
Alessandro Ferrante, Maurizio Memoli, Margherita N...
DATE
2009
IEEE
171views Hardware» more  DATE 2009»
14 years 2 months ago
Automatic generation of streaming datapaths for arbitrary fixed permutations
Abstract—This paper presents a technique to perform arbitrary fixed permutations on streaming data. We describe a parameterized architecture that takes as input n data points st...
Peter A. Milder, James C. Hoe, Markus Püschel