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» Generation of compact test sets with high defect coverage
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VLSID
2005
IEEE
131views VLSI» more  VLSID 2005»
14 years 7 months ago
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Sh...
VLSID
2000
IEEE
135views VLSI» more  VLSID 2000»
13 years 11 months ago
Performance and Functional Verification of Microprocessors
We address the problem of verifying the correctness of pre-silicon models of a microprocessor. We touch on the latest advances in this area by considering two different aspects of...
Pradip Bose, Jacob A. Abraham
DATE
2008
IEEE
121views Hardware» more  DATE 2008»
14 years 1 months ago
A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy
We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy, or more generally, a suboptimality in the synthe...
Irith Pomeranz, Sudhakar M. Reddy
ICCD
2004
IEEE
122views Hardware» more  ICCD 2004»
14 years 4 months ago
Quality Improvement Methods for System-Level Stimuli Generation
Functional verification of systems is aimed at validating the integration of previously verified components. It deals with complex designs, and invariably suffers from scarce re...
Roy Emek, Itai Jaeger, Yoav Katz, Yehuda Naveh
TACAS
2009
Springer
122views Algorithms» more  TACAS 2009»
14 years 2 months ago
Test Input Generation for Programs with Pointers
Software testing is an essential process to improve software quality in practice. Researchers have proposed several techniques to automate parts of this process. In particular, sym...
Dries Vanoverberghe, Nikolai Tillmann, Frank Piess...