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IPPS
2007
IEEE
14 years 2 months ago
Optimization and evaluation of parallel I/O in BIPS3D parallel irregular application
This paper presents the optimization and evaluation of parallel I/O for the BIPS3D parallel irregular application, a 3-dimensional simulation of BJT and HBT bipolar devices. The p...
Rosa Filgueira, David E. Singh, Florin Isaila, Jes...
ISCA
2007
IEEE
192views Hardware» more  ISCA 2007»
14 years 2 months ago
Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite
The recently released SPEC CPU2006 benchmark suite is expected to be used by computer designers and computer architecture researchers for pre-silicon early design analysis. Partia...
Aashish Phansalkar, Ajay Joshi, Lizy Kurian John
ISVLSI
2007
IEEE
230views VLSI» more  ISVLSI 2007»
14 years 2 months ago
A Methodology and Toolset to Enable SystemC and VHDL Co-simulation
The new design challenges imposed by the increasing difficulties of today’s electronic systems obligated designers to develop new methodologies. System-level design and Platfor...
Richard Maciel, Bruno Albertini, Sandro Rigo, Guid...
ICCS
2007
Springer
14 years 1 months ago
Multilingual Interfaces for Parallel Coupling in Multiphysics and Multiscale Systems
Abstract. Multiphysics and multiscale simulation systems are emerging as a new grand challenge in computational science, largely because of increased computing power provided by th...
Everest T. Ong, Jay Walter Larson, Boyana Norris, ...
DATE
2006
IEEE
120views Hardware» more  DATE 2006»
14 years 1 months ago
Soft delay error analysis in logic circuits
— In this paper, we present an analysis methodology to compute circuit node sensitivity due to charged particle induced delay (timing) errors, Soft Delay Errors (SDE). We define...
Balkaran S. Gill, Christos A. Papachristou, Franci...