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» Glitch Analysis and Reduction in Register Transfer Level
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GLVLSI
2003
IEEE
119views VLSI» more  GLVLSI 2003»
14 years 27 days ago
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
ALMOB
2006
135views more  ALMOB 2006»
13 years 7 months ago
P-value based visualization of codon usage data
Two important and not yet solved problems in bacterial genome research are the identification of horizontally transferred genes and the prediction of gene expression levels. Both ...
Peter Meinicke, Thomas Brodag, Wolfgang Florian Fr...
ICCD
2006
IEEE
138views Hardware» more  ICCD 2006»
14 years 4 months ago
Delay and Area Efficient First-level Cache Soft Error Detection and Correction
—Soft error rates are an increasing problem in modern VLSI circuits. Commonly used error correcting codes reduce soft error rates in large memories and second level caches but ar...
Karl Mohr, Lawrence Clark
FMICS
2006
Springer
13 years 11 months ago
Test Coverage for Loose Timing Annotations
Abstract. The design flow of systems-on-a-chip (SoCs) identifies several abstraction levels higher than the Register-Transfer-Level that constitutes the input of the synthesis tool...
Claude Helmstetter, Florence Maraninchi, Laurent M...
DSN
2004
IEEE
13 years 11 months ago
Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline
The progression of implementation technologies into the sub-100 nanometer lithographies renew the importance of understanding and protecting against single-event upsets in digital...
Nicholas J. Wang, Justin Quek, Todd M. Rafacz, San...