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MICRO
1997
IEEE
105views Hardware» more  MICRO 1997»
14 years 24 days ago
The Multicluster Architecture: Reducing Cycle Time Through Partitioning
The multicluster architecture that we introduce offers a decentralized, dynamically-scheduled architecture, in which the register files, dispatch queue, and functional units of t...
Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvon...
ISCA
2002
IEEE
95views Hardware» more  ISCA 2002»
14 years 1 months ago
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...
Ho-Seop Kim, James E. Smith
CP
2006
Springer
14 years 10 days ago
Global Optimization of Probabilistically Constrained Linear Programs
We consider probabilistic constrained linear programs with general distributions for the uncertain parameters. These problems generally involve non-convex feasible sets. We develo...
Shabbir Ahmed
ISLPED
1997
ACM
116views Hardware» more  ISLPED 1997»
14 years 24 days ago
Power reduction techniques for a spread spectrum based correlator
This paper presents the design of a low power spread spectrum correlator. We look at two major approaches and evaluate the best alternative for power reduction. We first consider...
David Garrett, Mircea R. Stan
DATE
2010
IEEE
139views Hardware» more  DATE 2010»
13 years 12 months ago
Finding reset nondeterminism in RTL designs - scalable X-analysis methodology and case study
Due to increases in design complexity, routing a reset signal to all registers is becoming more difficult. One way to solve this problem is to reset only certain registers and rely...
Hong-Zu Chou, Haiqian Yu, Kai-Hui Chang, Dylan Dob...