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» Good Programming in Transactional Memory
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ASPLOS
2011
ACM
12 years 11 months ago
Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory
Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such a...
Luke Dalessandro, François Carouge, Sean Wh...
MICRO
2010
IEEE
242views Hardware» more  MICRO 2010»
13 years 5 months ago
ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory
Advanced Synchronization Facility (ASF) is an AMD64 hardware extension for lock-free data structures and transactional memory. It provides a speculative region that atomically exec...
Jae-Woong Chung, Luke Yen, Stephan Diestelhorst, M...
POPL
2008
ACM
14 years 7 months ago
Semantics of transactional memory and automatic mutual exclusion
Software Transactional Memory (STM) is an attractive basis for the development of language features for concurrent programming. However, the semantics of these features can be del...
Andrew Birrell, Martín Abadi, Michael Isard...
PLDI
2009
ACM
14 years 2 months ago
Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory
Multicore designs have emerged as the mainstream design paradigm for the microprocessor industry. Unfortunately, providing multiple cores does not directly translate into performa...
Mojtaba Mehrara, Jeff Hao, Po-Chun Hsu, Scott A. M...
PPOPP
2009
ACM
14 years 5 days ago
Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions
Boosted transactions offer an attractive method that enables programmers to create larger transactions that scale well and offer deadlock-free guarantees. However, as boosted tran...
Chinmay Eishan Kulkarni, Osman S. Unsal, Adri&aacu...