403 search results - page 41 / 81 » Gradient clock synchronization |
MICRO
2002
IEEE
14 years 1 months ago
2002
IEEE
We describe the design, analysis, and performance of an on–line algorithm to dynamically control the frequency/voltage of a Multiple Clock Domain (MCD) microarchitecture. The MC...
FDL
2011
IEEE
12 years 8 months ago
2011
IEEE
—For the description of reactive systems, there is a large number of languages and formalisms, and depending on a particular application or design phase, one of them may be bette...
ICCAD
1993
IEEE
14 years 24 days ago
1993
IEEE
We present a design style and synthesis algorithm that encompasses both asynchronous and synchronous state machines. Our proposed design style not only supports generalized “bur...
DAC
2009
ACM
14 years 3 months ago
2009
ACM
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
ISPD
2005
ACM
14 years 2 months ago
2005
ACM
In the nanometer VLSI technology, the variation effects like manufacturing variation, power supply noise, temperature etc. become very significant. As one of the most vital nets...