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ICCD
2007
IEEE
206views Hardware» more  ICCD 2007»
14 years 5 months ago
SCAFFI: An intrachip FPGA asynchronous interface based on hard macros
Building fully synchronous VLSI circuits is becoming less viable as circuit geometries evolve. However, before the adoption of purely asynchronous strategies in VLSI design, globa...
Julian J. H. Pontes, Rafael Soares, Ewerson Carval...
PRDC
2007
IEEE
14 years 2 months ago
Assessment of Message Missing Failures in FlexRay-Based Networks
This paper assesses message missing failures in a FlexRay-based network. The assessment is based on about 35680 bit-flip fault injections inside different parts of the FlexRay com...
Vahid Lari, Mehdi Dehbashi, Seyed Ghassem Miremadi...
DSN
2005
IEEE
14 years 2 months ago
Design Time Reliability Analysis of Distributed Fault Tolerance Algorithms
Designing a distributed fault tolerance algorithm requires careful analysis of both fault models and diagnosis strategies. A system will fail if there are too many active faults, ...
Elizabeth Latronico, Philip Koopman
DFT
2006
IEEE
122views VLSI» more  DFT 2006»
14 years 9 days ago
Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design
The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synch...
Minsu Choi, Myungsu Choi, Zachary D. Patitz, Nohpi...
TVLSI
2010
13 years 3 months ago
A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors
A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost, flexible routing capability, and supports globally asynchronous loc...
Zhiyi Yu, Bevan M. Baas