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DATE
2010
IEEE
126views Hardware» more  DATE 2010»
14 years 1 months ago
Leveraging dominators for preprocessing QBF
— Many CAD for VLSI problems can be naturally encoded as Quantified Boolean Formulas (QBFs) and solved with QBF solvers. Furthermore, such problems often contain circuitbased in...
Hratch Mangassarian, Bao Le, Alexandra Goultiaeva,...
FM
2009
Springer
163views Formal Methods» more  FM 2009»
14 years 1 months ago
Analysis of a Clock Synchronization Protocol for Wireless Sensor Networks
We study a clock synchronization protocol for the Chess WSN. First, we model the protocol as a network of timed automata and verify various instances using the Uppaal model checker...
Faranak Heidarian, Julien Schmaltz, Frits W. Vaand...
CONCUR
1999
Springer
14 years 1 months ago
From Synchrony to Asynchrony
Abstract. We present an in-depth discussion of the relationships between synchrony and asynchrony. Simple models of both paradigms are presented, and we state theorems which guaran...
Albert Benveniste, Benoît Caillaud, Paul Le ...

Publication
130views
15 years 7 months ago
General Weighted Fairness and its Support in Explicit Rate Switch Algorithms
This paper gives a new definition of general weighted (GW) fairness and shows how this can achieve various fairness definitions, such as those mentioned in the ATM Forum TM 4.0 spe...
Bobby Vandalore, Sonia Fahmy, Raj Jain, Rohit Goya...
ICCV
2009
IEEE
15 years 1 months ago
Dimensionality Reduction and Principal Surfaces via Kernel Map Manifolds
We present a manifold learning approach to dimensionality reduction that explicitly models the manifold as a mapping from low to high dimensional space. The manifold is represen...
Samuel Gerber, Tolga Tasdizen, Ross Whitaker