227 search results - page 38 / 46 » Graph Rewriting for Hardware Dependent Program Optimizations |
ICSM
1994
IEEE
13 years 11 months ago
1994
IEEE
Although data pow analysis was first developed for use in compilers, its usefulness is now recognized in many software tools. Because of its compiler origins, the computation of d...
MICRO
2005
IEEE
14 years 1 months ago
2005
IEEE
Scheduling algorithms used in compilers traditionally focus on goals such as reducing schedule length and register pressure or producing compact code. In the context of a hardware...
IEEEPACT
2008
IEEE
14 years 1 months ago
2008
IEEE
The memory access limits the performance of stream processors. By exploiting the reuse of data held in the Stream Register File (SRF), an on-chip storage, the number of memory acc...
ISCA
2002
IEEE
14 years 13 days ago
2002
IEEE
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of th...
FPL
2001
Springer
14 years 14 hour ago
2001
Springer
System and processor architectures depend on changes in technology. Looking ahead as die density and speed increase, power consumption and on chip interconnection delay become incr...