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IPPS
1994
IEEE
13 years 11 months ago
Parallel Evaluation of a Parallel Architecture by Means of Calibrated Emulation
A parallel transputer-based emulator has been developed to evaluate the DDM--ahighlyparallel virtual shared memory architecture. The emulator provides performance results of a har...
Henk L. Muller, Paul W. A. Stallard, David H. D. W...
EUROPAR
2010
Springer
13 years 8 months ago
Thread Owned Block Cache: Managing Latency in Many-Core Architecture
Abstract. Shared last level cache is crucial to performance. However, multithread program model incurs serious contention in shared cache. In this paper, to reduce average cache ac...
Fenglong Song, Zhiyong Liu, Dongrui Fan, Hao Zhang...
WORDS
2003
IEEE
14 years 27 days ago
Foucault's Pendulum in the Distributed Control Lab
The ’Distributed Control Lab’ [6] at Hasso-PlattnerInstitute, University of Potsdam allows experimentation with a variety of physical equipment via the web (intra and internet...
Andreas Rasche, Peter Tröger, Michael Dirska,...
SIGGRAPH
1997
ACM
13 years 11 months ago
Interactive simulation of fire in virtual building environments
This paper describes the integration of the Berkeley Architectural Walkthrough Program with the National Institute of Standards and Technology’s CFAST fire simulator. The integ...
Richard W. Bukowski, Carlo H. Séquin
HPCA
2008
IEEE
14 years 8 months ago
Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems
Cache partitioning and sharing is critical to the effective utilization of multicore processors. However, almost all existing studies have been evaluated by simulation that often ...
Jiang Lin, Qingda Lu, Xiaoning Ding, Zhao Zhang, X...