Networks-on-Chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largel...
In this paper we present a probabilistic framework for the reduction in the uncertainty of a moving robot pose during exploration by using a second robot to assist. A Monte Carlo ...
Ioannis M. Rekleitis, Gregory Dudek, Evangelos E. ...
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, R...
Motivated by Lagrangian simulation of elastic deformation, we propose a new tetrahedral mesh generation algorithm that produces both high quality elements and a mesh that is well ...
Neil Molino, Robert Bridson, Joseph Teran, Ronald ...
We propose an economic model based on user utility to study the adoption of new network architectures such as IPv6. We use mathematical analysis and simulation studies to understa...
Dilip Antony Joseph, Nikhil Shetty, John Chuang, I...