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DATE
2007
IEEE
173views Hardware» more  DATE 2007»
14 years 2 months ago
Analytical router modeling for networks-on-chip performance analysis
Networks-on-Chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largel...
Ümit Y. Ogras, Radu Marculescu
ICRA
2003
IEEE
158views Robotics» more  ICRA 2003»
14 years 1 months ago
Probabilistic cooperative localization and mapping in practice
In this paper we present a probabilistic framework for the reduction in the uncertainty of a moving robot pose during exploration by using a second robot to assist. A Monte Carlo ...
Ioannis M. Rekleitis, Gregory Dudek, Evangelos E. ...
FPGA
2003
ACM
161views FPGA» more  FPGA 2003»
14 years 29 days ago
Implementation of BEE: a real-time large-scale hardware emulation engine
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, R...
IMR
2003
Springer
14 years 28 days ago
A Crystalline, Red Green Strategy for Meshing Highly Deformable Objects with Tetrahedra
Motivated by Lagrangian simulation of elastic deformation, we propose a new tetrahedral mesh generation algorithm that produces both high quality elements and a mesh that is well ...
Neil Molino, Robert Bridson, Joseph Teran, Ronald ...
CONEXT
2007
ACM
13 years 11 months ago
Modeling the adoption of new network architectures
We propose an economic model based on user utility to study the adoption of new network architectures such as IPv6. We use mathematical analysis and simulation studies to understa...
Dilip Antony Joseph, Nikhil Shetty, John Chuang, I...