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» HIDE : A Logic Based Hardware Development Environment
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ICCAD
1993
IEEE
81views Hardware» more  ICCAD 1993»
13 years 11 months ago
Inverter minimization in multi-level logic networks
In this paper, we look at the problem of inverter minimization in multi-level logic networks. The network is specified in terms of a set of base functions and the inversion opera...
Alok Jain, Randal E. Bryant
ECBS
2006
IEEE
203views Hardware» more  ECBS 2006»
13 years 11 months ago
The Feature-Architecture Mapping (FArM) Method for Feature-Oriented Development of Software Product Lines
Software product lines (PLs) are large, complex systems, demanding high maintainability and enhanced flexibility. Nonetheless, in the state of the art PL methods, features are sca...
Periklis Sochos, Matthias Riebisch, Ilka Philippow
SBACPAD
2008
IEEE
249views Hardware» more  SBACPAD 2008»
14 years 2 months ago
Processing Neocognitron of Face Recognition on High Performance Environment Based on GPU with CUDA Architecture
This work presents an implementation of Neocognitron Neural Network, using a high performance computing architecture based on GPU (Graphics Processing Unit). Neocognitron is an ar...
Gustavo Poli, José Hiroki Saito, Joã...
ISORC
2000
IEEE
14 years 1 days ago
A Distributed Real-Time Java System Based on CSP
CSP is a fundamental concept for developing software for distributed real-time systems. The CSP paradigm constitutes a natural addition to Object Orientation and offers higherorde...
Gerald H. Hilderink, Andry W. P. Bakkers, Jan F. B...
DATE
2004
IEEE
120views Hardware» more  DATE 2004»
13 years 11 months ago
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study
In this paper we describe how we applied a BIST-based approach to the test of a logic core to be included in System-on-achip (SoC) environments. The approach advantages are the ab...
Paolo Bernardi, Guido Masera, Federico Quaglio, Ma...