Sciweavers

495 search results - page 70 / 99
» HIDE : A Logic Based Hardware Development Environment
Sort
View
ICTAI
2003
IEEE
14 years 29 days ago
An Intelligent Early Warning System for Software Quality Improvement and Project Management
One of the main reasons behind unfruitful software development projects is that it is often too late to correct the problems by the time they are detected. It clearly indicates th...
Xiaoqing Frank Liu, Gautam Kane, Monu Bambroo
ISQED
2002
IEEE
106views Hardware» more  ISQED 2002»
14 years 18 days ago
Trading off Reliability and Power-Consumption in Ultra-low Power Systems
Critical systems like pace-makers, defibrillators, wearable computers and other electronic gadgets have to be designed not only for reliability but also for ultra-low power consu...
Atul Maheshwari, Wayne Burleson, Russell Tessier
ASYNC
1999
IEEE
110views Hardware» more  ASYNC 1999»
14 years 13 hour ago
Verification of Delayed-Reset Domino Circuits Using ATACS
This paper discusses the application of the timing analysis tool ATACS to the high performance, self-resetting and delayed-reset domino circuits being designed at IBM's Austi...
Wendy Belluomini, Chris J. Myers, H. Peter Hofstee
ASPDAC
2005
ACM
111views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Wave-pipelined on-chip global interconnect
— A novel wave-pipelined global interconnect system is developed for reliable, high throughput, on-chip data communication. We argue that because there is only a single signal pr...
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
SIGMETRICS
2002
ACM
115views Hardware» more  SIGMETRICS 2002»
13 years 7 months ago
Maximum likelihood network topology identification from edge-based unicast measurements
Network tomography is a process for inferring "internal" link-level delay and loss performance information based on end-to-end (edge) network measurements. These methods...
Mark Coates, Rui Castro, Robert Nowak, Manik Gadhi...