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HPCA
2009
IEEE
14 years 10 months ago
Adaptive Spill-Receive for robust high-performance caching in CMPs
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
Moinuddin K. Qureshi
VLSID
2003
IEEE
183views VLSI» more  VLSID 2003»
14 years 10 months ago
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks
We present an innovative design of an accurate, 2D DCT IDCT processor, which handles scaled and sub-sampled input blocks efficiently. In the IDCT mode, the latency of the processo...
Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van...
SAC
2010
ACM
14 years 4 months ago
A robust link-translating proxy server mirroring the whole web
Link-translating proxies are widely used for anonymous browsing, policy circumvention and WebVPN functions. These are implemented by encoding the destination URL in the path of th...
Ziqing Mao, Cormac Herley
MIDDLEWARE
2007
Springer
14 years 4 months ago
CAESAR: middleware for complex service-oriented peer-to-peer applications
Recent research advances in Peer-to-Peer (P2P) computing have enabled the P2P paradigm to be used for developing complex applications beyond file sharing and data storage. These ...
Lipo Chan, Shanika Karunasekera, Aaron Harwood, Eg...
ICPP
2006
IEEE
14 years 3 months ago
Data Transfers between Processes in an SMP System: Performance Study and Application to MPI
— This paper focuses on the transfer of large data in SMP systems. Achieving good performance for intranode communication is critical for developing an efficient communication s...
Darius Buntinas, Guillaume Mercier, William Gropp